A programmable logic device (PLD) reconfigures a circuit that can execute a predetermined process when configuration data for configuring the circuit that can execute the predetermined process is set in or written to an integrated circuit device in which a plurality of logic circuit elements, memory circuit elements, interconnects, switches, and the like are formed. A control circuit including processors and connected to a PLD sets or writes the configuration data for configuring a dedicated circuit in or to the PLD to configure the dedicated circuit in the PLD, to cause the dedicated circuit to execute a predetermined process. Such a PLD is an LSI, for example, a field programmable gate array (FPGA), which can reconfigure internal circuits into various logic circuits by rewriting configuration data.
When executing a process for a task, the control circuit configures, in the PLD, a logic circuit that executes a process for the task. When executing a process for a different task after the process for the task ends, the control circuit reconfigures, in the PLD, a logic circuit that executes a process for the different task. The PLD can be reconfigured into a plurality of logic circuits that execute processes for the respective tasks. The PLD is thus flexible about executable processes like software and can execute processes for a plurality of tasks at high speed using the dedicated logic circuit.
The PLD is disclosed in Japanese Laid-open Patent Publication No. 2010-2986, Japanese Laid-open Patent Publication No. 2006-333496, Japanese Laid-open Patent Publication No. 2004-21426, and Japanese Laid-open Patent Publication No. H11-184718.